Ogg-on-a-Chip Project

  Universitšt Stuttgart

  Computer Architecture  


An Ogg Vorbis audio decoder based on Xiph s Vorbis reference library has been designed as System-on-a-Chip using hardware/software co-design techniques. A demonstrator was built on the XESS XSV-800 prototyping board. The hard-ware architecture was built on the LEON SoC platform, which contained an open source SPARC-V8 architecture compatible processor, an AMBA bus, and the RTEMS embedded operating system. The audio interface hardware core from a previous project (DDM) was imported and reused. Vorbis stream decoding process was too computation-intensive for a real-time software-only decoder on the target platform. After an analysis of the Vorbis decoding algorithm, it was partitioned and the hardware part of the algorithm, MDCT, was designed as an AMBA com-patible core, implemented and added to the system. The final Vorbis audio player decoded Vorbis streams with the help of this MDCT-core.


The project officially started in January 2002 and finished in July 2002.


The project was master thesis of 2 students, Luis Azuara and Pattara Kiatisevi. We were studying in the INFOTECH program, University of Stuttgart, Germany. Our supervisor was Rainer Dorsch, division of Computer Architechture Division (Prof. Dr. Hans-Joachim Wunderlich), Computer Science faculty.


Our base location was in Stuttgart, Germany. However, Internet connects the world. Online discussions take place in the mailing list oggonachip at yahoogroups dot com. Click to subscribe to oggonachip.


Project has been finished! The final player ran with integerized Vorbis library (based on RC3) and RTEMS operating system on the LEON on the prototyping board with the help of the custom created MDCT hardware core.


Current status and News ticker

15.07.02 Master thesis report submitted. Project goal achieved.
04.07.02 Project was finished and presented at the University of Stuttgart.
...[sorry for long time no update]...
28.03.02 First 8-points-butterfly implemented on mdct core.
26.03.02 Future mdct core performs DMA using AHB.
26.03.02 Partition model optimized. Now the simulation takes 14.52 sec !! seems like the right partition :-)
19.03.02 The future mdct core is connected to APB bus on real hardware.
18.03.02 Updated partition model using mdct as TSIM modul, FPU and RTEMS. Result: 15 sec music played in 17 seconds
14.03.02 Ogg Vorbis decoder runs with RTEMS on TSIM using FPU
09.03.02 First partition model using mdct as TSIM modul,floating point emulation and RTEMS.Result:\15 sec music played in 130 seconds :-(
07.03.02 Ogg Vorbis decoder runs with RTEMS on TSIM without FPU
04.03.02 First try to run Ogg Vorbis decoder on the board using FPU. Result: 15 seconds of music decoded in 25 seconds with some errors.
01.03.02 Meiko FPU installed on the system and running on the board
22.02.02 Audio core improved for 2 channels Stereo and 16 bits/channelruns on XSV-800
21.02.02 FPU will be requiered for the project. Main candidate MEIKO-FPU from microSPARCII 
19.02.02 Ogg Vorbis decoder compiled for SPARC and running on TSIM
18.02.02 Music is played on RTEMS/LEON1-2.4.0
15.02.02 "Hello World" program runs on RTEMS/LEON1-2.4.0
14.02.02 "Hello World" program runs on RTEMS/TSIM
08.02.02 DDM runs on LEON1-2.4.0
07.02.02 Hardware and software are together. Music without compresion comes from the XSV-800
06.02.02 DDM runs on LEON1-2.3.7
31.01.02 The audio core of DDM will be used by Oggonachip
31.01.02 DDM is running on TSIM
10.12.01 The Digital Dictation Machine (DDM) is running on the XSV-800
10.12.01 TSIM selected as embedded-OS
19.11.01 Evaluation time is over! Project beginns

Next steps....

No future plan at the moment...


Our SourceForge project page
Mailing List at yahoogroups
Ogg Vorbis
LEON processor
LEOX Project

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